Due to aggressive process scaling, the raw bit error rate (BER) of NAND flash is becoming poorer and poorer. To maintain the same level of reliability, solid state drive (SSD) controllers are adopting error correction codes with soft decoding capability. For example, low density parity check (LDPC) codes have soft decoding capability. Error correction codes with soft decoding capability are more powerful in correcting errors but they use a soft input to the decoder. The soft input is in the form of a log likelihood ratio (LLR). Since conventional flash devices do not provide soft decision outputs, SSD controllers have to generate them using either hardware or software. Generating high quality LLRs is important for decoding results. There are many ways to generate LLRs. A simple and practical way is to pre-define LLR lookup tables (LUT) for different numbers of read retries. However, the distributions of LLRs can significantly change based on factors such as the number of program/erase cycles, retention, and read disturb.
It would be desirable to implement a method for dynamically generating LLRs for error recovery when predefined LLRs are suspected to be inaccurate.